4 Conclusion and Future Directions

interface language could be developed for other languages such as Verilog or even a Larch-based speciication. A parser would be developed that translates the VSPEC interface for each of these languages into a general abstract syntax tree. Constraint checking and other analysis could be performed on the general AST independent of the original language of the speciication. Tools to synthesize designs in each of these languages and others would be developed. In this scenario, the current work on VSPEC would be only a small part of the overall picture. This general abstract syntax tree will take several years to develop, but it is a long term goal of the current VSPEC research. The current reality of this research is that there are advantages to declaratively specifying a digital system. VHDL does not really allow this type of speciication. VSPEC extends VHDL to allow declarative speciications. A design utilizing VSPEC can be analyzed to ensure constraints are sat-issed. The abstract syntax tree can be used to synthesize behavioral VHDL and an implementation of the system speciied with VSPEC. Figure 4: Abstract syntax tree for multiplexor design. used to implement the VSPEC code. The user selects one architecture and modiies it to implement the speciic VSPEC speciication. Case-Based Reasoning is another technique being investigated. This technique also uses a library of potential behavioral implementations, but the selection and modiication are done by the program. An architecture is chosen from the library based on the similarity between the library architecture and the current problem 7, 1]. Transformation rules are then used to modify the selected architecture to implement the VSPEC speciication. Application of formal synthesis techinques is possible given the VSPEC speciicaiton methodology. Currently, we are implementing an interface from the VSPEC abstract syntax tree representation to KIDS, a deductive synthesis tool 9]. KIDS formally synthesizes algorithms from domain theories and general algorithm theories. It accepts speciications of pre-and post-conditions, and domain information and uses formal techniques to synthesize correct algorithms. The VSPEC project is currently at a very early stage in its development. The initial deenition of the language is complete and a parser has been developed to translate a VSPEC speciication into its representation in the abstract syntax tree. The next phase of the research will explore tactics to utilize the abstract syntax tree. A constraint checker is being developed to propagate constraints through the AST. It will be used to …